CS1: Processor Architecture and Operating Systems
Von Neumann vs Harvard, Fetch-Decode-Execute cycle, ALU, registers, pipelining, RISC vs CISC, memory management.
Von Neumann vs Harvard, Fetch-Decode-Execute cycle, ALU, registers, pipelining, RISC vs CISC, memory management.
Question:
Explain the Fetch-Decode-Execute cycle step-by-step with register transfers.
Model Solution & Mark Scheme:
1. Fetch: PC contents copied to MAR (MAR ← [PC]). PC incremented (PC ← [PC] + 1). Instruction fetched from RAM via data bus into MDR (MDR ← [[MAR]]). Instruction moved to CIR (CIR ← [MDR]). 2. Decode: CIR splits instruction into opcode and operand; Control Unit decodes. 3. Execute: ALU executes arithmetic/logic or data is loaded/stored; flags updated.
Q1: Explain the significance of Processor Architecture and Operating Systems in A-Level examination contexts.
Answer: Demonstrate clear conceptual understanding of Processor Architecture and Operating Systems, defining core terminology and citing relevant principles or case examples.
Q2: Evaluate key arguments or methodologies concerning Processor Architecture and Operating Systems.
Answer: Contrast competing perspectives, discuss empirical evidence or theoretical limitations, and synthesize a balanced, well-reasoned conclusion.